🔬 RESEARCH
- Hobbyist embeds a 32-bit RISC-V CPU inside Qwen's model weights for internal instruction execution
A developer built a 32-bit RISC-V CPU that lives inside Qwen's model weights, letting the model execute instructions internally.- Reddit user LatentSpacer demonstrated a 32-bit RISC-V CPU implemented directly inside Qwen's model weights, so the model can execute instructions internally rather than only emitting text.
- The approach could have implications for tool calling and computer use, where models need to run code as part of reasoning.
- It lands alongside a broader RISC-V-plus-Qwen push: Alibaba's XuanTie C950 RISC-V processor runs Qwen3.8-27B at over 30 tokens/second with a 1.9-second time-to-first-token on CPU cores alone, no GPU or binary translation layer.
- The C950 achieves this via its Attached Matrix Extension (8 TOPS per Tensor Processing Engine, FP16 down to INT4) and the open-sourced SHL/csi-nn2 operator library; figures are for a 64-core target configuration, not shipping silicon.
- If general-purpose RISC-V cores can serve a 27B model at reading speed, accelerator-free on-premises and edge inference becomes viable for a class of workloads.